features n -3db bandwidth of 1.1ghz n 325psec rise and fall times n 14db gain, 50 input and output n low distortion, linear phase n 1.4:1 vswr (output, dc-1.1ghz) n direct replacement for clc104 applications n digital and wideband analog communications n radar, if and rf processors n fiber optic drivers and receivers n photomultiplier preamplifiers general description the KH104 linear amplifier represents a significant advance in linear amplifiers. proprietary design techniques have yielded an amplifier with 14db of gain and a -3db bandwidth of dc to 1100mhz. gain flatness to 750mhz of ?.4db coupled with excellentvswr and phase linearity gives outstanding pulse fidelity and low signal distortion. designed for 50 systems, the KH104 is very easy to use, requiring only properly bypassed power supplies for operation. this translates to time and cost savings in all stages of design and production. fast rise time, low overshoot and linear phase make the KH104 ideal for high speed pulse amplification.these properties plus low distortion combine to produce an amplifier well suited to many communi-cations applications. with a 1.1ghz bandwidth, the KH104 can handle the fastest digital traffic, even when the demodulation scheme or the digital coding format requires that dc be maintained. it is also ideal for traditional video amplifier applications such as radar or wideband analog communications systems. these same characteristics make the KH104 an excellent choice for use in fiber optics systems, on either the transmitting or receiving end of the fiber. the low group delay distortion insures that pulse integrity will be maintained. as a photomultiplier tube pre-amp, its fast response and quick overload recovery provide for superior system performance. the KH104 is constructed using thin film resistor/ bipolar transistor technology, and is available in the following versions: KH104ai -25 to +85? 14-pin double-wide dip KH104 dc to 1.1ghz linear amplifier rev. 1a january 2004 KH104 11 v o 13 -v r 14 +v r 4 v in * ground 12 offset
adjust +5.4v
reg 1 +v cc -5.4v
reg 2 *pins 3, 5-10 case is ground 0.01 2.2 2.2 0.01 -15v +15v 39 0.01 v in v o 4 3,5-10 12 14 13 KH104 1 2 11 capacitance if f 0.01 0.01 39 offset
adjust 10k -15v +15v basic circuit diagram equivalent circuit diagram www.cadeka.com
data sheet KH104 2 rev. 1a january 2004 parameters conditions typ min & max ratings units sym ambient temperature KH104ai +25 min max frequency domain response = -3db bandwidth 0dbm out 1100 1000 mhz ssbw 10dbm out 1050 mhz ssbw = non-inverting gain (note 1) @ 100mhz 14.2 13.8 14.9 db = gain flatness dc - 750mhz 0.4 -0.6 +0.6 db linear phase deviation dc - 600mhz 1.5 3 lpd group delay 600 ps gd reverse isolation dc - 750mhz 40 db rini 750mhz - 1100mhz 35 db riin input return loss dc - 750mhz 18 db 750mhz - 1100mhz 11 db output return loss dc - 750mhz 17 db 750mhz - 1100mhz 10 db time domain response rise and fall time 1v step 325 375 ps trs (10% to 90%) 2v step 375 450 ps trl settling time to 0.8% 1v step 1.2 ns ts overshoot 1v step 3 % os overload recovery v inpeak = 0.5v 1.2 1.6 ns or noise and distortion response = 2nd harmonic distortion 0dbm, 100mhz 47 -dbc hd2 = 3rd harmonic distortion 0dbm, 100mhz 53 -dbc hd3 = 2nd harmonic distortion 10dbm, 100mhz 40 30 -dbc hd2 = 3rd harmonic distortion 10dbm, 100mhz 43 35 -dbc hd3 3rd order intermolulation intercept 100mhz 26 +dbm 2-tone, 1mhz separation 500mhz 17 equivalent input noise voltage 10hz to 1200mhz 55 db noise figure 11 db usable dynamic range 100mhz 71 db 500mhz 65 db static, dc performance input bias current note 2 80 280 a ibn input bias current (drift) note 2 0.6 2.0 a/ ibn output offset voltage note 3 50 250 mv output offset voltage (drift) note 3 375 625 v/ * supply current no load 54 60 ma icc supply rejection ratio 1khz 55 db psrr min/max ratings are based on product characterization and simulation. individual parameters are tested as noted. outgoing quality levels are determined from tested parameters. absolute maximum ratings notes v cc 9v to 16v i o 40ma input voltage 0.5v junction temperature +175 operating temperature ai: -25c to +85 storage temperature -65c to +150c KH104 electrical characteristics ( t a = +25c, v cc = ?5v, r l = 50 , r s = 50 ; unless specified) 1. nominal gain only - gain variation over temperature is 0.1db. 2. input offset voltage = (input bias current) x (r s || 50 ). 3. output offset can be adjusted to zero with an external potentiometer Csee ?ducing dc offset 4. * ai 100% tested at 25. = ai sample tested at 25.
KH104 data sheet rev. 1a january 2004 3 KH104 performance characteristics ( t a = +25, v cc = ?5v, r l = 50 , r s = 50 ; unless specified) forward gain and phase | s 2 1 | ( d b ) 16 14 8 frequency (mhz) 0 260 520 780 1.04g 1.3g 12 10 s 21 s 2 1 ( d e g ) 180 0 540 -180 -360 |s 21 | p o = 0dbm reverse gain and phase | s 1 2 | ( - d b ) 0 20 80 40 60 s 12 s 1 2 ( d e g ) 360 180 -360 0 -180 |s 12 | p o = 0dbm frequency (mhz) 0 260 520 780 1.04g 1.3g input return loss | s 1 1 | ( - d b ) 0 20 80 40 60 frequency (mhz) 0 260 520 780 1.04g 1.3g output return loss | s 2 2 | ( - d b ) 0 20 80 40 60 frequency (mhz) 0 260 520 780 1.04g 1.3g pulse response i n p u t ( 4 0 m v / d i v ) o u t p u t ( 2 0 0 m v / d i v ) 500ps/div k input output 2nd and 3rd harmonic distortion d i s t o r t i o n ( d b c ) frequency (hz) k -20 -30 -80 100k 1m 10m 100m 1g -40 -50 2nd 3rd p o = 0dbm -60 -70 2-tone, 3rd order intermod. intercept i n t e r c e p t p o i n t ( d b m ) frequency (mhz) k 30 25 0 0 200 400 600 1000 20 15 10 5 800 noise spectral density n o i s e l e v e l ( d b m / h z ) frequency (hz) k -120 -170 10 1k 100k 1g -130 -140 -150 -160 10m -1db gain compression power output (dbm) frequency (mhz) 16 0 0 2 00 4 00 1 000 1 2 8 4 600 8 00 usable dynamic range d y n a m i c r a n g e ( d b ) frequency (mhz) k 72 70 60 0 200 400 600 1000 68 66 64 62 800 power supply rejection ratio p s r r ( d b ) frequency (hz) k 70 60 10 1 10 100 1k 1m 50 40 30 20 10k 100k relative bandwidth vs. case temp. r e l a t i v e b a n d w i d t h ( % ) case temperature ( c) 105 100 80 0 20 40 60 140 95 90 85 80 100 120 p d = 1.6w
ca = 30 c/w
data sheet KH104 4 rev. 1a january 2004 pc board layout considerations proper layout of printed circuit boards is important to achieve optimum performance of a circuit operating inthe 1ghz frequency range. use of microstripline is recommended for all signal-carrying paths and low resistance, low inductance signal return and bypass paths should be used. to keep the impedance of these paths low, use as much ground plane as possible. ground plane also serves to increase the flow of heat out of the package. the KH104 has three types of connections: signal paths (input and output), dc inputs (supplies and offset adjust), and grounds. 50 microstrip is recommended for connection to the input (pin 4) and output (pin 11). microstrip on a doublesided pc board consists of a ground plane on one side of the board and a constant- width signal-carrying trace on the other side of the board. for 1/16g10 or fr-- pc board material, a 0.1?ide trace will have a 50 characteristic impedance. the ground plane beneath the signal trace must extend at least one trace width on either side of the trace. also, all traces (including ground) should be kept at least one trace width from the signal carrying traces. to keep power supply noise and oscillations from appearing at the amplifier output, all supply pins should be capacitively bypassed to ground. the power supply pins (1 and 2) are the inputs to a pair of voltage regulators whose outputs are at pins 13 and 14. it is recommended that 0.01 f or larger ceramic capacitors be connected from pins 1, 2, 13 and 14 to ground, within 0.2of the pins. a 1 f or larger solid tantalum capacitor to ground is required within 3of pins 1 and 2, and for good low frequency performance, solid tantalum capacitors of at least 15 f should be connected from pins 13 and 14 to ground within 3of the pins. use 0.025or wider traces for the supply lines. the offset adjust pin (12) also requires bypassing; a 0.01 f or larger ceramic capacitor to ground within 0.2of the pinis recommended. grounding is the final layout consideration. pins 3 and 5- 10 should all be connected to a ground plane whichshould cover as much of one side of the board around the amplifier as possible. reducing dc offset dc offset of the KH104 may be adjusted by applying a dc voltage to the amplifiers offset adjust pin (12). the simplest method is shown in figure 1. using this method of offset adjust it is possible to vary the output offset by approximately 400mv. this simple adjustment has no effect on the offset drift characteristics of the KH104. figure 1: basic circuit if lower offset and offset drift are required, a low frequency op amp may be used in conjunction with the KH104 in a composite configuration. the suggested circuit appears in figure 2. its method of operation is to compare an attenuated version of the output signal to the input signal and apply a correcting voltage at the offset adjust pin. a compensation capacitor c s reduces the bandwidth of the op amp correction circuit to limit the op amps effect on the KH104 to frequencies below f 45 , the frequency at which the op amp has 45db of open loop gain. using anlm108, f 45 is about 7hz with c s = 0.1 f. thus the op amp can correct dc and low frequency errors below f 45 , without affecting KH104 performance above f 45 . also note that the noise performance of the op amp will dom-inate below f 45 . figure 2: composite amplifier with an lm108 op amp in this composite configuration, input offset is typically 2mv and drift is 15mv/. at frequencies well below f 45 , the composite gain is equal to (1 + 49.9k/(r a + r b )) and the output impedance is 0.01 2.2 2.2 0.01 -15v +15v 39 0.01 v in v o 4 3,5-10 12 14 13 KH104 1 2 11 capacitance if f 0.01 0.01 39 offset
adjust 10k -15v +15v v in v o 4 12 KH104 lm108 k 0.01 0.01 2k c s 0.01 -15v +15v 0.01 r c 9.76k 6 7 8 4 2 3 11 49.9k r a 11.8k r b 1k r l 50 capacitance in f r c = (r a + r b ) || 49.9k
rev. 1a january 2004 5 KH104 data sheet voltage across the regulator of 3.6v and a minimum regulator current of 10ma will satisfy the regulator dropout voltage and current limits. given the maximum anticipated power supply voltages, the shunt resistor should be calculated to yield a 35ma current from that voltage to the regulated voltage of 5.4v. this will leave 10ma through the regulator at the minimum quiescent current of 45ma. the regulator input voltages may be reduced directly by dropping the voltage supplies, or, if that option is not available, using either a zener or resistive dropping element in series with the supply. if a series dropping element is used, the decoupling capacitors must appear on pins 1 and 2 of the KH104. figure 3 shows two possible power reduction circuits from fixed 15v supplies. several methods of decreasing the thermal resistance from case to ambient are possible. with no heat paths other than still air at 25, the thermal resistance from case to ambient for the KH104 is about 40/w. when placed in a printed circuit board with all ground pins soldered into a ground plane 1x 1.5?the thermal resistance drops to about 30/w in this configuration, the case rise will be 30 for 9v supplies and 50? for 16v supplies. this results in maximum allowable ambient temperatures of 110 and 90? respectively. if higher operating temperatures are required, heat sinking of the package is recommended. figure 3: reducing power dissipation very low. as the signal frequency increases beyond f 45 , the op amp loses influence and the KH104 gain and output impedance dominate. to ensure a smooth transition and matched gain at all frequencies, adjust r b for a minimum op amp output swing with a 0.1v pp sinewave input (to the KH104) at the frequency f 45 . since the KH104 has a 50 output impedance, its output voltage is a function of the load impedance (a v ~ _ 10r l /(r l + 50)), whereas the gain of the compos- ite amplifier at low frequencies and dc is relatively independent of the load impedance, due to the high open-loop gain of the op amp. thus, to avoid gain mismatching and phase non-linearity, use the composite amplifier only if the load impedance is constant from dc to at least 10(f 45 ). use of a composite amplifier reduces input offset voltage and its corresponding drift, but has no effect on input bias current. this current is converted to an input voltage by the resistance to ground seen at the amplifier input and the voltage appears, amplified, at the output. typical input offset voltage due to the bias current is 2mv and input offset drift is approximately 15mv/. thermal considerations the KH104 case must be maintained at or below 140. note that because of the amplifier design, power dissipa-tion remains fairly constant, independent of the load or drive level. therefore, standard derating is not possible. there are two ways to keep the case temperature low. the first is to keep the amount of power dissipated inside the package to a minimum and the second is to get the heat out of the package quickly by reducing the thermal resistance from case to ambient. a large portion of the heat dissipated inside the package is in the voltage regulators. at the minimum +9v supply level the regulators dissipate 390mw and at the maximum 16v supply level they dissipate 1.2w. the amplifier itself dissipates a fairly constant 600mw (55ma x 10.8v). reducing the power dissipation of the internal regulators will go far towards reducing the internal junction temperatures without impacting the so performance. reducing either the input supply voltages (on pins 1 and 2) and/or shunting the regulator current through external resistors (from pins 1 to 14 and pins 2 to 13) are both effective means towards significantly reducing the internal power dissipation. a minimum 2.2 f 0.01f v in 115 d1 5.6v +15v 2.2 f 0.01f 115 d2 5.6v -15v 1 2 13 14 v o + + 2.2 f 0.01 f v in 200 +15v 2.2 f 0.01 f 200 -15v 1 2 13 14 v o + + 60 60 d1, d2 in4734 nominal, no load p d ~ C 760mw nominal, no load p d ~ C 900mw
KH104 package dimensions data sheet KH104 0.050 r (typ) 0.060 r (typ) 0.016 C0.020 (0.41 C0.51) 0.140 C0.180 (3.56 C4.57) 0.590 C0.610 (14.99 C15.49) 0.740 C0.760 (18.80 C19.30) 0.740 C0.760 (18.80 C19.30) 0.590 C0.610 (14.99 C15.49) 0.090 C0.110 (2.29 C2.79) 0.240 C0.260 (6.10 C6.60) life support policy cadekas products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of cadeka microcircuits, inc. as used herein: 1. life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. cadeka does not assume any responsibility for use of any circuitry described, and cadeka reserves the right at any time without notice to change said circuitry and specifications. www.cadeka.com ?2004 cadeka microcircuits, llc
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